Senior VLSI Integration Engineer

• Top-Level Integration: Own the integration of complex mixed-signal SoCs, merging digital control cores, analog blocks, and power management units into a single digital-top environment.
• Multi-Disciplinary Coordination: Translate system-level hardware, board, and power electronics constraints into VLSI chip-level integration specifications.
• Floorplanning & Construction: Define top-level chip architecture, power grid distribution, pin placement, and digital floorplanning to optimize area, timing, and signal integrity.
• Mixed-Signal Verification: Set up and maintain behavioral and circuit-level simulation environments to verify top-level connectivity, power-up sequences, and analog-digital interfaces.
• Cross-Functional Collaboration: Partner with packaging, test, and PCB engineers to ensure the silicon design aligns with final board-level thermal, electrical, and physical constraints.

• Education: B.Sc. or M.Sc. in Electrical Engineering, Microelectronics, or a related technical discipline.
• Experience: 8+ years of hands-on experience in VLSI chip integration, digital-top mixed-signal design flows, or physical design.
• Technical Domain: Deep understanding of digital-top integration methodologies, RTL design (Verilog/SystemVerilog), and automated chip assembly scripts.
• Interface Knowledge: Solid understanding of mixed-signal boundaries, including ADC/DAC interfaces, gate driver control signals, and analog-to-digital loop interactions.
• Tooling Proficiency: Mastery of industry-standard EDA tools for digital floorplanning, synthesis, and hierarchical physical design (e.g., Innovus, IC Compiler II).

The following skills and experiences are considered a strong advantage:

• System-Level Capabilities: Experience looking at the "big picture" to map board-level application requirements directly to silicon architecture.
• Power Electronics Knowledge: Familiarity with SMPS topologies (Buck, Boost, LLC), transient behaviors, and how digital control loops interact with power stages.
• Analog VLSI Insight: Strong understanding of analog circuit layouts, noise isolation, guard rings, and substrate noise mitigation.
• Advanced Packaging Experience: Knowledge of modern packaging technologies (e.g., flip-chip, wire-bonding, multi-chip modules) and their impact on high-current/high-voltage silicon layout.
• Advanced Floorplanning: Proven track record of handling complex, non-standard digital floorplanning constrained by high-current paths and sensitive analog domains.